Progressively larger capacity semiconductor memories of all types are being fabricated as higher bit densities and smaller cell designs are realized. In 1972 efforts were being made to produce 4 kilobit (4 Kbit) Dynamic Random Access Memories (DRAMs) and by 1983 256 Kbit devices became available. One megabit (1 Mbit) DRAM devices were introduced by 1987, 4 Mbit devices will be sold widely by 1990 and 16 Mbit devices are currently in design stages. Memory devices with 64 Mbit, 256 Mbit or even larger capacities may be manufactured during the 1990's.
Despite rapid increases in the capacities of DRAMs, Static Random Access Memories (SRAMs) and nonvolatile memory devices, there continues to be a need to form microprocessor based systems with larger memory capacities than available in a single device. Memory modules provide a standard solution to the problem of meeting ever-increasing memory capacity requirements. Generally, a memory module comprises plural discrete memory devices mounted on a common substrate. For example, a 256 Kbit memory module can be configured with four 64 Kbit DRAMs to form a 64 K.times.4 memory, i.e., a composite memory with four I/O paths for storing 64 K four bit words. Similarly, .times.8 modules handle eight bit words while .times.9 modules accommodate a parity bit as well as eight data bits.
Memory modules of much higher capacity can be formed with 256 Kbit and 1 Mbit devices. By way of example, DRAM module TMO24EAD9, manufactured by Texas Instruments Incorporated, incorporates nine 1 Mbit DRAMs to provide a 1,048,576.times.9 memory organization in a 30-pin Single-In-Line Package (SIP). In this memory module, the Column Address Strobe (CAS) control lines on eight of the devices are connected in common to the same control pin to provide eight parallel data lines for .times.8 operation. A separate CAS control line is provided for the ninth device, which stores the parity bit.
In many memory applications, it is important to assure data accuracy by performing a parity check for each word of data. Thus it is common for module designs to include additional memory circuitry to store parity information. Module architectures can be formed to accommodate parity data for larger word sizes, e.g., 16, 32 or 64 bit data I/O. An example is DRAM module TM256KBC36, also manufactured by Texas Instruments Incorporated, which comprises eight 1 Mbit DRAMs and four 256 Kbit DRAMs to provide a .times.36 organization. The storage depth of this module, i.e., the number of words which can be stored on the module, is 256 K. In addition to providing a 36 bit word length with a 256 K depth, this architecture provides an even greater depth for shorter words. That is, the TM256KBC36 is a .times.36 module capable of storing either 262,144 36-bit words, 524,288 18-bit words or 1,048,576 9-bit words.
The TM256KBC36, schematically illustrated in FIG. 1, is configured as a single-in-line package with four groups of memory devices. Each group includes two 256 K.times.4 DRAMs and one 256 K.times.1 DRAM. Each group provides 256 K of storage depth for eight bits of data and a parity bit. The CAS control lines of all devices in the same group are wired to a common group control pin. Thus each of four group control pins is associated with a different 9-bit data group stored in three of the 12 module devices. This enables read/write operations in integer multiples of 9-bit words.
Although modules such as the TM256KBC36 provide a convenient and flexible means for expanding memory capacity, it is well known that the advantages of such are accompanied by an increased cost per bit of memory over the cost per bit of a discrete device. A portion of these increased costs is inherent to the formation of a complex circuit with multiple integrated circuit devices. The cost of packaging and testing a module also increases in proportion to the number of discrete components on the board. In addition, significant costs are associated with development and fabrication of memory boards which accommodate a large number of integrated circuits. In particular, designs which minimize thermal stress and mechanical vibration problems become more costly as the weight, physical size and power requirements of a module increase. Surface mount technology, which reduces module size and fabrication costs, has provided only a partial solution to some of these problems.
In view of these factors and a growing demand for progressively larger capacity memory systems, there is a desire in the art to further reduce the physical size and cost per bit of memory modules.